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01/10/16 NJU6680 -1- 128-common x 128-segment 4-level gray scale bitmap lcd driver general description the NJU6680 is a 128-common x 128-segment 4-level gray scale bit map lcd driver to display graphics or characters. it contains 32,768-bit display data ram, microprocessor interface circuits, instruction decoder, and common and segment drivers. an image data from cpu through the serial or 8-bit parallel interface are stored into the 32,768-bit internal display data ram and are displayed on the lcd panel through the commons and segments drivers. the NJU6680 features 4-level gray scale display function creating 4 types of gray scale (white / light gray / dark gray / black) and black & white display function. the NJU6680 contains a built-in osc circuit for reducing external components. and it features partial display function containing selectable active display block and optimizing the duty cycle ratio. this function dramatically reduces the operating current, setting the optimum boosted voltage combined with a programmable voltage booster circuit and an electrical variable resistor. as result, it reduces the operating current. the operating voltage from 2.0v to 3.0v and low operating current are suitable for small size battery operation items. features direct correspondence of display data ram to lcd pixel display method ? 4 level gray scale / black & white display data ram ? 32,768 bits ;( 128-com x 128-seg) x 2bit lcd drivers ? 128-common and 128 segment direct connection to 8-bit microprocessor interface for both of 68 and 80 type mpu serial interface (si, scl, rs, cs) partial display function easy vertical scroll by setting the start line address of over size display data ram programmable bias ratio selection ; 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11, 1/12 bias useful instruction sets status read, display data write, column address set, page address set, initial display line set, initial com 0 line set, display on/off, entire display on/off, reverse display on/off, n-line inversion set, n-line inversion off, adc select, com scan direction select, internal resistor ratio set, power control set, partial display duty set, lcd bias set, boost level set, contrast level set, power save mode on, power save mode off, internal oscillator on, display data length set, reset, frc & pwm set, grey scale mode set display mode set. power supply circuit for lcd; programmable booster circuits (6 times maximum, voltage boosting polarity : positive voltage (v ss common), voltage adjust circuit, voltage follower (x 4)) precision electrical variable resistance (64 step) low operating current i out1 =400 a (typ.) operating voltage 2.0 to 3.0 v lcd driving voltage 6.0 to 18.0v package outline bumped chip / tcp / cof c-mos technology ( substrate : p ) NJU6680cl preliminary package outline
2 NJU6680 - 2 - pad location chip center :x=0um,y=0um chip size :x=13.11m,y=3.08mm chip thickness :675um +/- 30um bump size :40um x 83um pad pitch :60um (min) bump height :15um (typ) bump material :au voltage boosting polarity : positive voltage (v ss common) substrate : p dummy 63 dummy 64 dummy 60 dummy 61 dummy 62 dummy 34 c 29 c 91 s 127 x y c 93 c 92 test5 dummy 33 v dd c 4 + test 1 dummy 18 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 v ss v ss v ss c 3 + c 1 - c 1 + ps 1 c 2 - c 2 + v dd v dd v out dummy 28 vr v dd dummy 26 e vext intrs v 3 v dd v ss ref c 5+ v 2 v 0 v 4 v 1 rw c 28 dummy 27 dummy 25 dummy 22 dummy 21 dummy 20 dummy 19 osc 1 v ss v dd v ss v ci v dd v dd v dd v dd v dd v dd v dd v ss rs v dd v dd v dd res cs v ss v ss v ss v dd v dd v dd ps 0 v ss v ss v ss v dd v dd v dd dummy 17 dummy 16 dummy 15 dummy 14 dummy 13 dummy 12 dummy 11 dummy 10 dummy 9 dummy 8 dummy 7 dummy 6 dummy 5 dummy 4 dummy 3 dummy 2 dummy 1 test4 c 27 c 26 c 25 c 94 c 95 dummy 59 dummy 58 dummy 57 dummy 56 dummy 55 dummy 54 dummy 53 dummy 52 dummy 51 dummy 50 dummy 49 dummy 48 dummy 47 c 90 c 89 c 64 s 0 c 0 dummy 35 dummy 36 dummy 37 dummy 40 dummy 41 dummy 42 dummy 43 dummy 44 dummy 45 dummy 46 c 27 c 28 dummy 32 dummy 31 c 29 c 30 c 31 c 61 c 62 c 63 dummy 30 dummy 29 test3 test2
NJU6680 -3 - pad coordinates chip size 13.11 3.08mm(chip center x=0 m, y=0 m) pad no. terminal x(um) y(um) pad no. terminal x(um) y(um) 1 dummy 1 -6302 -1384 51 db 2 -930 -1384 2 dummy 2 -6242 -1384 52 db 3 -710 -1384 3 dummy 3 -6182 -1384 53 db 4 -490 -1384 4 dummy 4 -6122 -1384 54 db 5 -270 -1384 5 dummy 5 -6062 -1384 55 db 6 -50 -1384 6 dummy 6 -6002 -1384 56 db 7 170 -1384 7 dummy 7 -5942 -1384 57 v dd 362 -1384 8 dummy 8 -5882 -1384 58 v dd 422 -1384 9 dummy 9 -5822 -1384 59 v dd 482 -1384 10 dummy 10 -5762 -1384 60 v dd 542 -1384 11 dummy 11 -5702 -1384 61 v ci 739 -1384 12 dummy 12 -5642 -1384 62 v ss 957 -1384 13 dummy 13 -5582 -1384 63 v out 1067 -1384 14 dummy 14 -5522 -1384 64 c5 + 1284 -1384 15 dummy 15 -5462 -1384 65 c3 + 1547 -1384 16 dummy 16 -5402 -1384 66 c1 - 1810 -1384 17 dummy 17 -5342 -1384 67 c1 + 2073 -1384 18 dummy 18 -5282 -1384 68 c2 + 2336 -1384 19 v dd -5222 -1384 69 c2 - 2599 -1384 20 v dd -5162 -1384 70 c4 + 2862 -1384 21 v dd -5102 -1384 71 v dd 3070 -1384 22 test 1 -4897 -1384 72 v dd 3130 -1384 23 v ss -4712 -1384 73 v dd 3190 -1384 24 v ss -4652 -1384 74 ref 3377 -1384 25 v ss -4592 -1384 75 v ss 3557 -1384 26 ps 0 -4397 -1384 76 vext 3754 -1384 27 v dd -4209 -1384 77 v dd 3952 -1384 28 v dd -4149 -1384 78 intrs 4132 -1384 29 v dd -4089 -1384 79 v ss 4315 -1384 30 ps 1 -3892 -1384 80 v 4 4425 -1384 31 v ss -3707 -1384 81 v 3 4535 -1384 32 v ss -3647 -1384 82 v 2 4645 -1384 33 v ss -3587 -1384 83 v 1 4755 -1384 34 cs -3394 -1384 84 v 0 4974 -1384 35 res -3165 -1384 85 vr 5084 -1384 36 v dd -2982 -1384 86 v ss 5287 -1384 37 v dd -2922 -1384 87 v dd 5377 -1384 38 v dd -2862 -1384 88 osc 1 5558 -1384 39 rs -2669 -1384 89 dummy 19 5757 -1384 40 r/w -2440 -1384 90 dummy 20 5817 -1384 41 v ss -2257 -1384 91 dummy 21 5877 -1384 42 v ss -2197 -1384 92 dummy 22 5937 -1384 43 v ss -2137 -1384 93 dummy 23 5997 -1384 44 e -1940 -1384 94 dummy 24 6057 -1384 45 v dd -1760 -1384 95 dummy 25 6117 -1384 46 v dd -1700 -1384 96 dummy 26 6177 -1384 47 v dd -1640 -1384 97 dummy 27 6237 -1384 48 v dd -1580 -1384 98 dummy 28 6297 -1384 49 db 0 -1370 -1384 99 test 2 6400 -1273 50 db 1 -1150 -1384 100 dummy 29 6400 -1213
4 NJU6680 - 4 - pad no. terminal x(um) y(um) pad no. terminal x(um) y(um) 101 test 3 6400 -1153 151 dummy 43 5730 1384 102 dummy 30 6400 -1033 152 dummy 44 5670 1384 103 com 63 6400 -973 153 dummy 45 5610 1384 104 com 62 6400 -913 154 dummy 46 5550 1384 105 com 61 6400 -853 155 com 27 5490 1384 106 com 60 6400 -793 156 com 26 5430 1384 107 com 59 6400 -733 157 com 25 5370 1384 108 com 58 6400 -673 158 com 24 5310 1384 109 com 57 6400 -613 159 com 23 5250 1384 110 com 56 6400 -553 160 com 22 5190 1384 111 com 55 6400 -493 161 com 21 5130 1384 112 com 54 6400 -433 162 com 20 5070 1384 113 com 53 6400 -373 163 com 19 5010 1384 114 com 52 6400 -313 164 com 18 4950 1384 115 com 51 6400 -253 165 com 17 4890 1384 116 com 50 6400 -193 166 com 16 4830 1384 117 com 49 6400 -133 167 com 15 4770 1384 118 com 48 6400 -73 168 com 14 4710 1384 119 com 47 6400 -13 169 com 13 4650 1384 120 com 46 6400 47 170 com 12 4590 1384 121 com 45 6400 107 171 com 11 4530 1384 122 com 44 6400 167 172 com 10 4470 1384 123 com 43 6400 227 173 com 9 4410 1384 124 com 42 6400 287 174 com 8 4350 1384 125 com 41 6400 347 175 com 7 4290 1384 126 com 40 6400 407 176 com 6 4230 1384 127 com 39 6400 467 177 com 5 4170 1384 128 com 38 6400 527 178 com 4 4110 1384 129 com 37 6400 587 179 com 3 4050 1384 130 com 36 6400 647 180 com 2 3990 1384 131 com 35 6400 707 181 com 1 3930 1384 132 com 34 6400 767 182 com 0 3870 1384 133 com 33 6400 827 183 seg 0 3810 1384 134 com 32 6400 887 184 seg 1 3750 1384 135 com 31 6400 947 185 seg 2 3690 1384 136 com 30 6400 1007 186 seg 3 3630 1384 137 com 29 6400 1067 187 seg 4 3570 1384 138 com 28 6400 1127 188 seg 5 3510 1384 139 dummy 31 6400 1187 189 seg 6 3450 1384 140 dummy 32 6400 1247 190 seg 7 3390 1384 141 dummy 33 6400 1307 191 seg 8 3330 1384 142 dummy 34 6270 1384 192 seg 9 3270 1384 143 dummy 35 6210 1384 193 seg 10 3210 1384 144 dummy 36 6150 1384 194 seg 11 3150 1384 145 dummy 37 6090 1384 195 seg 12 3090 1384 146 dummy 38 6030 1384 196 seg 13 3030 1384 147 dummy 39 5970 1384 197 seg 14 2970 1384 148 dummy 40 5910 1384 198 seg 15 2910 1384 149 dummy 41 5850 1384 199 seg 16 2850 1384 150 dummy 42 5790 1384 200 seg 17 2790 1384
NJU6680 -5 - pad no. terminal x(um) y(um) pad no. terminal x(um) y(um) 201 seg 18 2730 1384 251 seg 68 -270 1384 202 seg 19 2670 1384 252 seg 69 -330 1384 203 seg 20 2610 1384 253 seg 70 -390 1384 204 seg 21 2550 1384 254 seg 71 -450 1384 205 seg 22 2490 1384 255 seg 72 -510 1384 206 seg 23 2430 1384 256 seg 73 -570 1384 207 seg 24 2370 1384 257 seg 74 -630 1384 208 seg 25 2310 1384 258 seg 75 -690 1384 209 seg 26 2250 1384 259 seg 76 -750 1384 210 seg 27 2190 1384 260 seg 77 -810 1384 211 seg 28 2130 1384 261 seg 78 -870 1384 212 seg 29 2070 1384 262 seg 79 -930 1384 213 seg 30 2010 1384 263 seg 80 -990 1384 214 seg 31 1950 1384 264 seg 81 -1050 1384 215 seg 32 1890 1384 265 seg 82 -1110 1384 216 seg 33 1830 1384 266 seg 83 -1170 1384 217 seg 34 1770 1384 267 seg 84 -1230 1384 218 seg 35 1710 1384 268 seg 85 -1290 1384 219 seg 36 1650 1384 269 seg 86 -1350 1384 220 seg 37 1590 1384 270 seg 87 -1410 1384 221 seg 38 1530 1384 271 seg 88 -1470 1384 222 seg 39 1470 1384 272 seg 89 -1530 1384 223 seg 40 1410 1384 273 seg 90 -1590 1384 224 seg 41 1350 1384 274 seg 91 -1650 1384 225 seg 42 1290 1384 275 seg 92 -1710 1384 226 seg 43 1230 1384 276 seg 93 -1770 1384 227 seg 44 1170 1384 277 seg 94 -1830 1384 228 seg 45 1110 1384 278 seg 95 -1890 1384 229 seg 46 1050 1384 279 seg 96 -1950 1384 230 seg 47 990 1384 280 seg 97 -2010 1384 231 seg 48 930 1384 281 seg 98 -2070 1384 232 seg 49 870 1384 282 seg 99 -2130 1384 233 seg 50 810 1384 283 seg 100 -2190 1384 234 seg 51 750 1384 284 seg 101 -2250 1384 235 seg 52 690 1384 285 seg 102 -2310 1384 236 seg 53 630 1384 286 seg 103 -2370 1384 237 seg 54 570 1384 287 seg 104 -2430 1384 238 seg 55 510 1384 288 seg 105 -2490 1384 239 seg 56 450 1384 289 seg 106 -2550 1384 240 seg 57 390 1384 290 seg 107 -2610 1384 241 seg 58 330 1384 291 seg 108 -2670 1384 242 seg 59 270 1384 292 seg 109 -2730 1384 243 seg 60 210 1384 293 seg 110 -2790 1384 244 seg 61 150 1384 294 seg 111 -2850 1384 245 seg 62 90 1384 295 seg 112 -2910 1384 246 seg 63 30 1384 296 seg 113 -2970 1384 247 seg 64 -30 1384 297 seg 114 -3030 1384 248 seg 65 -90 1384 298 seg 115 -3090 1384 249 seg 66 -150 1384 299 seg 116 -3150 1384 250 seg 67 -210 1384 300 seg 117 -3210 1384
6 NJU6680 - 6 - pad no. terminal x(um) y(um) pad no. terminal x(um) y(um) 301 seg 118 -3270 1384 351 dummy 59 -6270 1384 302 seg 119 -3330 1384 352 dummy 60 -6400 1307 303 seg 120 -3390 1384 353 dummy 61 -6400 1247 304 seg 121 -3450 1384 354 dummy 62 -6400 1187 305 seg 122 -3510 1384 355 com 92 -6400 1127 306 seg 123 -3570 1384 356 com 93 -6400 1067 307 seg 124 -3630 1384 357 com 94 -6400 1007 308 seg 125 -3690 1384 358 com 95 -6400 947 309 seg 126 -3750 1384 359 com 96 -6400 887 310 seg 127 -3810 1384 360 com 97 -6400 827 311 com 64 -3870 1384 361 com 98 -6400 767 312 com 65 -3930 1384 362 com 99 -6400 707 313 com 66 -3990 1384 363 com 100 -6400 647 314 com 67 -4050 1384 364 com 101 -6400 587 315 com 68 -4110 1384 365 com 102 -6400 527 316 com 69 -4170 1384 366 com 103 -6400 467 317 com 70 -4230 1384 367 com 104 -6400 407 318 com 71 -4290 1384 368 com 105 -6400 347 319 com 72 -4350 1384 369 com 106 -6400 287 320 com 73 -4410 1384 370 com 107 -6400 227 321 com 74 -4470 1384 371 com 108 -6400 167 322 com 75 -4530 1384 372 com 109 -6400 107 323 com 76 -4590 1384 373 com 110 -6400 47 324 com 77 -4650 1384 374 com 111 -6400 -13 325 com 78 -4710 1384 375 com 112 -6400 -73 326 com 79 -4770 1384 376 com 113 -6400 -133 327 com 80 -4830 1384 377 com 114 -6400 -193 328 com 81 -4890 1384 378 com 115 -6400 -253 329 com 82 -4950 1384 379 com 116 -6400 -313 330 com 83 -5010 1384 380 com 117 -6400 -373 331 com 84 -5070 1384 381 com 118 -6400 -433 332 com 85 -5130 1384 382 com 119 -6400 -493 333 com 86 -5190 1384 383 com 120 -6400 -553 334 com 87 -5250 1384 384 com 121 -6400 -613 335 com 88 -5310 1384 385 com 122 -6400 -673 336 com 89 -5370 1384 386 com 123 -6400 -733 337 com 90 -5430 1384 387 com 124 -6400 -793 338 com 91 -5490 1384 388 com 125 -6400 -853 339 dummy 47 -5550 1384 389 com 126 -6400 -913 340 dummy 48 -5610 1384 390 com 127 -6400 -973 341 dummy 49 -5670 1384 391 dummy 63 -6400 -1033 342 dummy 50 -5730 1384 392 test 4 -6400 -1153 343 dummy 51 -5790 1384 393 dummy 64 -6400 -1213 344 dummy 52 -5850 1384 394 test 5 -6400 -1273 345 dummy 53 -5910 1384 346 dummy 54 -5970 1384 347 dummy 55 -6030 1384 348 dummy 56 -6090 1384 349 dummy 57 -6150 1384 350 dummy 58 -6210 1384
NJU6680 -7 - block diagram com 0 - - - com 63 com 127 - - - com 64 seg 0 - - - - - - - seg 127 v dd v ss v 0 to v 4 c1 + /c1 - c2 + /c2 - c3 + v out v ci vr ps 1 cs e d 7 (si) d 6 (scl) d 5 to d 0 res ps 0 r/w rs reset mpu interface instruction decoder status busy flag bus holder internal bus line multiplexer column address register column address counter column address decoder oscillator display timing line counter line address decoder low address decoder display data ram 128 x 128 x 2 = 32,768-bits display data latch segment drivers common drivers common drivers shift register shift register voltage converter common timing osc 1 voltage regulator voltage followers internal power circuits page address register common direction v 0 vext ref intrs c4 + c5 +
8 NJU6680 - 8 - terminal description ? power supply no. terminal description 19-21, 27-29, 36-38, 45-48, 57-60, 71-73, 77,87 v dd power supply 23-25, 31-33, 41-43, 62,75, 79,86 v ss ground, 0v ? internal power circuits no. terminal description 61 v ci voltage converter input terminal 63 v out voltage converter output terminal 84 83 82 81 80 v 0 v 1 v 2 v 3 v 4 lcd driving voltage terminals ? when the internal power circuits are used, the lcd driving voltages (v 0 to v 4 ) are enabled by the ?power control set? instruction and an lcd bias ratio is selected by the ?lcd bias set? instruction. ? when the internal power circuits are not used, the external voltages (v 0 to v 4 ) are required on these terminals. the external voltages should be maintained in the relationship: v ss < v 4 < v 3 < v 2 < v 1 < v 0 . 67 66 c1 + c1 - capacitor terminals for voltage converter 68 69 c2 + c2 - capacitor terminals for voltage converter 65 c3 + capacitor terminal for voltage converter 70 c4 + capacitor terminal for voltage converter 64 c5 + capacitor terminal for voltage converter 85 vr v0 voltage adjustment terminal 74 ref internal or external reference voltage select terminal ?h?: internal ?l?: external 76 vext external reference voltage input terminal ? this terminal is valid when the ref terminal is connected to ?l?. 78 intrs internal resistor select terminal ?h?: internal ?l?: external
NJU6680 -9 - ? mpu interface circuits no. terminal description 26 ps 0 30 ps 1 parallel or serial interface select terminal ps 0 =?l?, ps 1 =?l?: 3-line serial ps 0 =?l?, ps 1 =?h?: 4-line serial ps 0 =?h?, ps 1 =?l?: 80 type mpu parallel interface ps 0 =?h?, ps 1 =?h?: 68 type mpu parallel interface 34 cs chip select terminal active ?l? 56-49 d 7 -d 0 data bus terminals parallel interface: d 7 to d 0 serial interface: si (d 7 terminal), scl (d 6 terminal) 39 rs register select terminal ? this signal distinguishes instruction data or display data when the lsi is used in the 4-line serial or parallel interface mode. rs=?h?: d 7 to d 0 are display data rs=?l?: d 7 to d 0 are instruction data 44 e (rd) 68 type mpu: active ?h? 80 type mpu: active ?l? 40 r/w (wr) 68 type mpu: r/w=?h?: read operation r/w=?l?: write operation 80 type mpu: active ?l? 35 res reset terminal active ?l? 88 osc 1 osc terminal ? when the internal oscillator is used, the external resistor, rf, is required between this terminal and the v dd . rf=270k ? : frame frequency=165hz (typ.) ? lcd drivers no. terminal description 182-155, 138-103, 311-338, 355-390 com 0 -- com 127 common (row) drivers com 0 -com 127 182-310 seg 0 -- seg 127 segment (column) drivers seg 0 -seg 127 ? dummy no. terminal description 1-18, 89-98, 100,102 139-154, 339-354, 391,393 dummy 1 -- dummy 64 no connections. dummy pads ? test terminals no. terminal description 22,99, 101,392, 394 test 1 -- test 5 no connections. used for maker test
10 NJU6680 - 10 - functional description (1) description of each blocks (1-1) busy flag (bf) the bf is used to indicate whether the lsi is busy or not. during the busy status, the lsi cannot accept any instruction except the ?status read? instruction, which reads out the bf through the d 7 terminal. when the cycle time (tcyc) mentioned in ?ac characteristics? is satisfied, the bf is not required after each instruction so that it is possible to improve the process performance of an mpu. (1-2) initial display line register the initial display line register is used to specify the ddram line address corresponding to the com 0 by the ?initial display line set? instruction. it is used not only for normal display but also vertical scrolling and page switching displays without changing the display data in the ddram. (1-3) line counter the line counter is used to provide the ddram line address. the line address is initialized whenever the polarity of an internal frame signal (fr) is switched, and then it is counted up in synchronization of a common timing signal. (1-4) column address counter an mpu can access only 7-bit [c6:c0] ?column address? by the ?column address lsb set? and ?column address msb set? instructions. when both 4-bit lsb and 3-bit msb data is set into the column address register, 8-bit ?internal column address? is established in the lsi as illustrated in the following figure, and accordingly, 2-bit display data must be written for each pixel with two successive bytes. the column address automatically increases by 1 (+1) after each 2-byte display data and wraps around to the column address (00) h in the same page after the last column is addressed. the assignment of the column address for the segment drivers can be reversed by the ?adc set? instruction. segment outputs seg 0 seg 1 seg 2 seg 3 ?. seg 124 seg 125 seg 126 seg 127 internal column address (00) h (01) h (02) h (03) h (04) h (05) h (06) h (07) h ?. (f8) h (f9) h (fa) h (fb) h (fc) h (fd) h (fe) h (ff) h column address (adc=0) (00) h (01) h (02) h (03) h ?. (7c) h (7d) h (7e) h (7f) h display data 1 1 0 0 0 1 1 0 ?. 0 1 1 0 1 1 0 0 display image ?. column address (adc=1) (7f) h (7e) h (7d) h (7c) h ?. (03) h (02) h (01) h (00) h display data 0 0 1 1 1 0 0 1 ?. 1 0 0 1 0 0 1 1 display image ?. (1-5) page address register the page address register is used to provide the ddram page address. (1-6) display data ram (dd ram) the ddram is capable of 32,768-bit, composed of 128-line by 256-column addressable array, for the 4-gray scale display with 128x128 pixels. in the normal display mode, the display data ?1? turns on and ?0? turns off an lcd pixel. in the reverse display mode, ?1? turns off and ?0? turns on.
NJU6680 -11 - page address data display pattern line address common outputs d 0 00 h com 0 d 1 01 h com 1 d 2 02 h com 2 d 3 page 0 03 h com 3 d 4 04 h com 4 d 5 05 h com 5 d 6 06 h com 6 d 3 ,d 2 ,d 1 ,d 0 (0,0,0,0) d 7 07 h com 7 d 0 08 h com 8 d 1 09 h com 9 d 2 0a h com 10 d 3 page 1 0b h com 11 d 4 0c h com 12 d 5 0d h com 13 d 6 0e h com 14 d 3 ,d 2 ,d 1 ,d 0 (0,0,0,1) d 7 0f h com 15 d 0 10 h com 16 d 1 11 h com 17 d 2 12 h com 18 : : : : : : : : : : : : : : : : d 5 75 h com 117 d 6 76 h com 118 : : : : d 7 77 h com 119 d 0 78 h com 120 d 1 79 h com 121 d 2 7a h com 122 d 3 page 15 7b h com 123 d 4 7c h com 124 d 5 7d h com 125 d 6 7e h com 126 d 3 ,d 2 ,d 1 ,d 0 (1,1,1,1) d 7 7f h com 127 internal column address 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d - - - - - - - - - - - - - - - - - - - - - f c f d f e f f adc=0 00 01 02 03 04 05 06 [c6:c0] 7e 7f column address adc=1 7f 7e 7d 7c 7b 7a 79 [c6:c0] 01 00 segment outputs 0 1 2 3 4 5 6 - - - - - - - - - - - - - - - - - - - - - 126 127 fig.1 display data ram (ddram) map this is an example for initial display line (06) h. initial=(06) h second byte first byte
12 NJU6680 - 12 - (1-7) common direction register the common direction register is used to select a common scan direction by setting the s 0 in the ?com scan direction select? instruction. s 0 com scan direction 0 com 0 to com 127 1 com 127 to com 0 (1-8) reset circuit the reset circuit is used to initialize the lsi to the following default status by setting the res terminal to ?0? level. default status by using of the res terminal 1. page address : (0) page 2. column address : (00) h 3. com scan direction : s 0 =0 4. adc select : s 0 =0 5. initial display line : (00) h 6. initial com0 line : (00) h 7. display on/off : off 8. reverse display on/off : off 9. entire display on/off : off 10. n-line inversion on/off : off 11. partial display duty ratio : 1/128 duty 12. power control register : (vc,vr,vf)=(0,0,0) 13. boost level : 3x boost 14. contrast level : 32 level 15. lcd bias : 1/12 bias 16. internal resistor ratio : 1+rb/ra=2.3 17. internal oscillator on/off : off 18.power save mode on/off : off 19. display data length : (0,0,0,0) 20. white mode set : off 21. white palette register : (0,0,0,0) 22. light gray mode set : off 23. light gray palette register : (0,0,0,0) 24. dark gray mode set : off 25. dark gray palette register : (1,1,1,1) 26. black mode set : off 27. black palette register : (1,1,1,1) 28. frc & pwm mode : 4-frame, 9-level 29. display mode set : gray scale mode the res terminal is usually connected to the mpu?s reset terminal in order that the lsi is initialized at the same timing of the mpu reset. the reset time must be at least 10us or longer, as mentioned in ?dc characteristics?. the lsi will return to normal operation after about 1us from the rising edge of the rest signal. in case that an external power supply is used for the lcd driving voltage, the res terminal is required to be maintained in the ?0? level when the external power supply is turned on. the ?reset? instruction in table 3 cannot be substituted for the reset operation by the res terminal. it can execute only 1,2,5,14,16,19 to 28 items listed above.
NJU6680 - 13 - (1-9) lcd display circuits (a) common and segment drivers the common and segment drivers are used to generate lcd driving waveforms in accordance with the combination of display data, common timing signal (cl) and internal frame signal (fl). (b) display timing generator the display timing generator is used to generate the common timing signal (cl) and the internal frame signal (fr). the fr signal adopts the 2-frame ac driving method, in which the fr signal is toggled to alternate the crystal polarization on an lcd panel. it toggles on every frame in the default setting or once every n frames in the n-line inversion mode setting, as illustrated in fig.2-1 and fig.2-2. (c) display data latch circuit the display data latch circuit is used to temporally store the 128-bit display data transferred from the ddram and output these display data onto the segment drivers in synchronization of the cl signal. the output timing for the display data, from display latch circuits to segment drivers, is independent of the access timing from mpu to ddram. as a result, the lcd display is not affected by the ddram access. the ?display on/off?, ?reverse display on/off? and ?entire display on/off? instructions control the display data in the display data latch circuit, however they do not change the display data in the ddram. fig.2-1 lcd driving waveforms 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 cl fr com 0 com 1 segn duty cycle ratio=1/128
14 NJU6680 - 14 - fig. 2-2. lcd diving waveforms in the n-line inversion mode (d) oscillator the internal oscillator is used to create internal clocks for the display timing signals (cl, fr) and the voltage converter. 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 cl fr com 0 com 1 segn n=5, duty cycle ratio=1/128
NJU6680 - 15 - (e) internal power circuits the internal power circuits are composed of the voltage converter, voltage regulator with 64-level evr, and voltage followers. the status of the internal power circuits is arranged by the ?power control set? instruction, as shown in table 1. for this arrangement, the part of the internal power circuits can be used in combination with an external power supply, as shown in table 2. the internal power circuits require the optimum values for the passive components, such as v 0 to v 4 capacitors and external feedback resistors in accordance with an lcd panel; and accordingly should be evaluated by using of actual lcd module samples to decide these values. table 1. power control set bits portions status vc voltage converter 1: on 0: off vr voltage regulator 1: on 0: off vf voltage followers 1: on 0: off table 2. power supply combinations instruction power supply circuits output terminals combination vc vr vf voltage converter voltage regulator voltage followers v out v 0 v 1 -v 4 using all internal power circuits 1 1 1 on on on open open open using voltage regulator and voltage followers 0 1 1 off on on external open open using voltage followers 0 0 1 off off on open external open using only external power supply 0 0 0 off off off open external external note) de coupling capacitors on the v 0 to v 4 terminals are required when the voltage followers are enabled.
16 NJU6680 - 16 - power supply circuits example fig. 3. power circuits configuration v out c5+ c4+ c3+ c2+ c2- c1- c1- vr v 0 v 1 v 2 v 3 v 4 intrs voltage converter v out c5+ c4+ c3+ c2+ c2- c1- c1- vr v 0 v 1 v 2 v 3 v 4 intrs voltage converter v out c5+ c4+ c3+ c2+ c2- c1- c1- vr v 0 v 1 v 2 v 3 v 4 intrs external power supply v out c5+ c4+ c3+ c2+ c2- c1- c1- vr v 0 v 1 v 2 v 3 v 4 intrs external power supply using all internal power circuits and internal resistors using all internal power circuits and external resistors using only voltage regulator and internal resistors using only external power supply
NJU6680 - 17 - (2) instructions the NJU6680 distinguishes the data on the data bus d 0 to d 7 as an instruction by combination of rs and r/w signals. the decoding of the instruction and exection performes with only high speed internal timing without relation to the external clock. in case of the serial interface, the data input as msb(d 7 ) first serially. table.3-1, 3-2 shows the instruction codes of the NJU6680 table 3-1. instruction codes code instruction rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 descriptions (a) status read 0 1 busy on res 0 0 0 0 0 (b) display data write 1 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 column address lsb set 0 0 0 0 0 0 c 3 c 2 c 1 c 0 lower 4-bit (c) column address msb set 0 0 0 0 0 1 0 c 6 c 5 c 4 upper 3-bit (d) internal resistor ratio set 0 0 0 0 1 0 0 r 2 r 1 r 0 (e) power control set 0 0 0 0 1 0 1 vc vr vf (f) initial display line set (dual instructions) 0 0 0 0 0 * 1 l 6 0 l 5 0 l 4 0 l 3 0 l 2 * l 1 * l 0 set initial display line mode specify line address (g) initial com 0 line set (dual instructions) 0 0 0 0 0 * 1 c 6 0 c 5 0 c 4 0 c 3 1 c 2 * c 1 * c 0 set initial com 0 line mode specify line address (h) partial display duty set (dual instructions) 0 0 0 0 0 d 7 1 d 6 0 d 5 0 d 4 1 d 3 0 d 2 * d 1 * d 0 set partial display mode specify duty cycle ratio (i) n-line inversion set (dual instructions) 0 0 0 0 0 * 1 * 0 * 0 n 4 1 n 3 1 n 2 * n 1 * n 0 set n-line inversion mode specify the number of n-line (j) lcd bias set 0 0 0 1 0 1 0 b 2 b 1 b 0 (k) boost level set 0 0 0 1 1 0 0 1 b 1 b 0 (l) contrast level set (dual instructions) 0 0 0 0 1 * 0 * 0 c 5 0 c 4 0 c 3 0 c 2 0 c 1 1 c 0 set contrast level mode specify contrast level (m) adc select 0 0 1 0 1 0 0 0 0 s 0 select segment direction (n) entire display on/off 0 0 1 0 1 0 0 1 0 e 0 e 0 =0: off, e 0 =1: on (o) reverse display on/off 0 0 1 0 1 0 0 1 1 r 0 r 0 =0: off, r 0 =1: on (p) power save mode on 0 0 1 0 1 0 1 0 0 1 power save mode (q) internal oscillator on 0 0 1 0 1 0 1 0 1 1 (r) display on/off 0 0 1 0 1 0 1 1 1 d 0 d 0 =0: off, d 0 =1: on (s) page address set 0 0 1 0 1 1 p 3 p 2 p 1 p 0 (t) com scan direction select 0 0 1 1 0 0 s 0 * * * select common direction (u) power save mode off 0 0 1 1 1 0 0 0 0 1 (v) reset 0 0 1 1 1 0 0 0 1 0 (w) n-line inversion off 0 0 1 1 1 0 0 1 0 0 (x) display data length set (dual instructions) 0 0 0 0 1 d 7 1 d 6 1 d 5 0 d 4 1 d 3 0 d 2 0 d 1 0 d 0 set display data length specify the data length (y) frc & pwm set 0 0 1 0 0 1 0 frc pwm 1 pwm 0 (*:don?t care)
18 NJU6680 - 18 - table 3-2. instruction codes code instruction rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 descriptions white mode set, 1st/2nd frame 0 0 1 wb 3 0 wb 2 0 wb 1 0 wb 0 1 wa 3 0 wa 2 0 wa 1 0 wa 0 specify mode & frame sets 4-bit pallet registers white mode set, 3rd/4th frame 0 0 1 wd 3 0 wd 2 0 wd 1 0 wd 0 1 wc 3 0 wc 2 0 wc 1 1 wc 0 specify mode & frame sets 4-bit pallet registers light gray mode set, 1st/2nd frame 0 0 1 lb 3 0 lb 2 0 lb 1 0 lb 0 1 la 3 0 la 2 1 la 1 0 la 0 specify mode & frame sets 4-bit pallet registers light gray mode set, 3rd/4th frame 0 0 1 ld 3 0 ld 2 0 ld 1 0 ld 0 1 lc 3 0 lc 2 1 lc 1 1 lc 0 specify mode & frame sets 4-bit pallet registers dark gray mode set, 1st/2nd frame 0 0 1 db 3 0 db 2 0 db 1 0 db 0 1 da3 1 da2 0 da1 0 da0 specify mode & frame sets 4-bit pallet registers dark gray mode set, 3rd/4th frame 0 0 1 dd 3 0 dd 2 0 dd 1 0 dd 0 1 dc 3 1 dc 2 0 dc 1 1 dc 0 specify mode & frame sets 4-bit pallet registers black mode set, 1st/2nd frame 0 0 1 bb 3 0 bb 2 0 bb 1 0 bb 0 1 ba 3 1 ba 2 1 ba 1 0 ba 0 specify mode & frame sets 4-bit pallet registers (z) black mode set, 3rd/4th frame 0 0 1 bd 3 0 bd 2 0 bd 1 0 bd 0 1 bc 3 1 bc 2 1 bc 1 1 bc 0 specify mode & frame sets 4-bit pallet registers (aa) display mode set 0 0 1 1 1 0 1 1 1 dm 0 dm 0 =0: gray scale mode dm 0 =1: black & white mode (bb) test mode 0 0 1 1 1 1 * * * * don?t use. (*:don?t care)
NJU6680 - 19 - (2-1) descriptions of the instruction codes (a) status read the ?status read? instruction is used to read out an lsi internal status. it is available only in the parallel interface mode. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 busy on res 0 0 0 0 0 busy 0: the lsi is idle. 1: the lsi is busy and cannot accept any instruction except the ?status read?. on 0: display off 1: display on res 0: the lsi is idle. 1: the lsi is executing the reset operation. (b) display data write the ?display data write? instruction is used to write display data into the ddram, which address is designated by the ?column address set? and ?page address set? instructions. the column address automatically increases by 1 (+1) after each 2-byte display data and wraps around to the column address 00 h in the same page after the last column is addressed. in case that the lsi is used in the 3-line serial interface mode, the ?display data length set? instruction is required before the ?display data write? instruction. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0 display data sequence for the display data writing page address set column address set display data write column + 1 data write continue? no yes
20 NJU6680 - 20 - (c) column address set the ?column address set? instruction is used to specify the column address for display data. it is required before the ?display data write? instruction. an mpu can access only 7-bit [c6:c0] ?column address? by the ?column address lsb set? and ?column address msb set? instructions. when both 4-bit lsb and 3-bit msb data is set into the column address register, 8-bit ?internal column address? is established in the lsi. for this reason, 2-bit display data must be written for each pixel with two successive bytes. the column address automatically increases by 1 (+1) after each 2-byte display data and wraps around to the column address 00 h in the same page after the last column is addressed, and therefore, the ddram can be continuously accessed without another ?column address set? instruction. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 0 0 0 c 3 c 2 c 1 c 0 lsb column address 0 0 0 0 0 1 0 c 6 c 5 c 4 msb column address c 6 c 5 c 4 c 3 c 2 c 1 c 0 column address internal column address 00 h 0 0 0 0 0 0 0 00 h 01 h 02 h 0 0 0 0 0 0 1 01 h 03 h : : : : : : : : : : : : : : : : : : fc h 1 1 1 1 1 1 0 7e h fd h fe h 1 1 1 1 1 1 1 7f h ff h (d) internal resistor ratio set the ?internal resistor ratio set? instruction is used to determine the internal resistor ratio (1+rb/ra) for the voltage regulator. for more information, refer to (3-3) ?setting for internal resistor ratio?. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 0 1 0 0 r 2 r 1 r 0 r 2 r 1 r 0 1+(rb/ra) 0 0 0 2.3 0 0 1 3.0 0 1 0 3.7 0 1 1 4.4 1 0 0 5.1 1 0 1 5.8 1 1 0 6.5 1 1 1 7.2 (e) power control set the ?power control set? instruction is used to configure the internal power circuits. for more information, refer to (3) ?internal power circuits?. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 0 1 0 1 vc vr vf vc vr vf 0 1 voltage converter off voltage converter on 0 1 voltage regulator off voltage regulator on 0 1 voltage followers off voltage followers on
NJU6680 - 21 - (f) initial display line set the ?initial display line set? instruction is used to specify the line address, which corresponds to the initial com 0 line (com 0 ). rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 0 0 0 0 * * set initial display line 0 0 * l 6 l 5 l 4 l 3 l 2 l 1 l 0 specify line address l 6 l 5 l 4 l 3 l 2 l 1 l 0 line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 : : : : : : : : 1 1 1 1 1 0 1 125 1 1 1 1 1 1 0 126 1 1 1 1 1 1 1 127 (g) initial com 0 line set the ?initial com 0 line set? instruction is specify the common driver, which starts scanning the display data in the ddram. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 0 0 0 1 * * set initial com 0 line 0 0 * c 6 c 5 c 4 c 3 c 2 c 1 c 0 specify initial com 0 c 6 c 5 c 4 c 3 c 2 c 1 c 0 initial com 0 0 0 0 0 0 0 0 com 0 0 0 0 0 0 0 1 com 1 0 0 0 0 0 1 0 com 2 : : : : : : : : 1 1 1 1 1 0 1 com 125 1 1 1 1 1 1 0 com 126 1 1 1 1 1 1 1 com 127 (h) partial display duty set the ?partial display duty set? instruction is used to specify the duty cycle ratio for the partial display. the lsi can be programmed to select not only the duty cycle ratio, but also the lcd bias ratio, boost level and contrast level by the instructions so that it is possible to optimize the lsi?s condition in accordance with the partial display status. for more information, refer to (7) ?partial display function?. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 0 0 1 0 * * set partial display duty 0 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 specify duty cycle ratio d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 duty 0 0 0 0 0 0 0 0 : : : : : : : : 0 0 0 0 1 1 1 1 invalid 0 0 0 1 0 0 0 0 1/16 : : : : : : : : : 1 0 0 0 0 0 0 0 1/128 1 0 0 0 0 0 0 1 : : : : : : : : 1 1 1 1 1 1 1 1 invalid
22 NJU6680 - 22 - (i) n-line inversion register set the ?n-line inversion register set? instruction is used to control the alternate rates of the crystal polarization on an lcd panel. in the n-line inversion mode, the fr signal toggles once every n frames, which number is selected in between 3 and 33 lines, and therefore, prevents a cross talk. if the n-line inversion is disabled by the ?n-line inversion mode off? instruction, the fr signal toggles by the frame. the number of the n-line should not be set to 1/2 of the display duty cycle ratio in order to avoid generating a dc bias when the partial display is used. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 0 0 1 1 * * set n-line inversion 0 0 * * * n 4 n 3 n 2 n 1 n 0 specify n-line number n 4 n 3 n 2 n 1 n 0 number of n-line 0 0 0 0 0 0 0 0 0 0 1 3 lines : : : : : : 1 1 1 1 0 32 lines 1 1 1 1 1 33 lines (j) lcd bias set the ?lcd bias set? instruction is used to select the lcd bias ratio. for more information, refer to (3-8) ?voltage followers?. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 0 1 0 b 2 b 1 b 0 b 2 b 1 b 0 bias 0 0 0 1/5 0 0 1 1/6 0 1 0 1/7 0 1 1 1/8 1 0 0 1/9 1 0 1 1/10 1 1 0 1/11 1 1 1 1/12 (k) boost level set the ?boost level set? instruction is used to select the multiple for the voltage converter. for detailed information, refer to (3-1) ?voltage converter?. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 1 0 0 1 b 1 b 0 b 1 b 0 boost 0 0 3x 0 1 4x 1 0 5x 1 1 6x (l) contrast level set the ?contrast level set? instruction is used to fine-tune the lcd driving voltage (v lcd ) in accordance with an lcd panel. for detailed information, refer to (3-2) ?voltage regulator?. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 0 0 0 0 0 1 set contrast level 0 0 * * c 5 c 4 c 3 c 2 c 1 c 0 specify contrast level
NJU6680 - 23 - (m) adc select the ?adc select? instruction is used to reverse the column address assignment for the segment drivers, so that it is possible to reduce the restriction for the placement of the lsi in an lcd module. for more information, refer to ?- connection between the lsi and lcd panel?. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 1 0 0 0 0 s 0 s 0 segment direction 0 seg 0 to seg 127 1 seg 127 to seg 0 (n) entire display on/off the ?entire display on/off? instruction is used to enable or disable the entire display, which turns on all pixels without changing the display data in the ddram. the ?entire display on/off? instruction has a priority over the ?reverse display on/off? instruction and the ?display on/off? instruction has the priority over the ?entire display on/off? instruction. as a result, even though the ?entire display on? can be accepted during the ?display off?, the visual state of the lcd panel does not change. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 1 0 0 1 0 e 0 e 0 mode 0 entire display off (normal) 1 entire display on (o) reverse display on/off the ?reverse display on/off? instruction is used to enable or disable the reverse display, which reverses the illumination of each pixel without changing the display data in the ddram. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 1 0 0 1 1 r 0 r 0 mode 0 reverse display off (normal) 1 reverse display on reverse display off (normal) display data 1 11 0010 0 illumination reverse display on display data 1 11 0010 0 illumination
24 NJU6680 - 24 - (p) power save mode on the ?power save mode on? instruction is used to enable the power save mode, where it is possible to reduce the power consumption down to stand-by current level. both of the lsi?s internal status and the display data in the ddram before the ?power save mode on? instruction are maintained during the power save mode, in which it is possible to access to the ddram. the internal status of the lsi in the power save mode is listed below. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 1 0 1 0 0 1 mode description power save mode oscillator off lcd power supply off com/seg outputs v ss (q) internal oscillator on the ?internal oscillator on? instruction is used to enable the internal oscillator. since the oscillator always turns off after the reset operation, this instruction must be executed for the initialization. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 1 0 1 0 1 1 (r) display on/off the ?display on/off? instruction is used to control the display on or off without changing the display data in the ddram. the ?display on/off? instruction has a priority over the ?entire display on/off? and ?reverse display on/off? instructions. accordingly, even though the ?entire display on? and ?reverse display on? instructions can be accepted during the ?display off?, the visual state of the lcd panel does not change. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 1 0 1 1 1 d 0 d 0 mode 0 display off 1 display on (s) page address set the ?page address set? instruction is used to specify the page address for display data. it is required before the ?display data write? instruction. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 1 1 p 3 p 2 p 1 p 0 (t) com scan direction select the ?com scan direction select? is used to select the com scan direction, so that it is possible to reduce the restriction for the placement of the lsi in an lcd module. for more information, refer to ?-connection between the lsi and lcd panel?. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 0 0 s 0 * * * s 0 com scan direction 0 com 0 to com 127 1 com 127 to com 0
NJU6680 - 25 - (u) power save mode off the ?power save mode off? instruction is used to release the lsi from the power save mode. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 1 0 0 0 0 1 (v) reset the ?reset? instruction is used to reset the lsi to the following status. it doesn?t change the display data in the ddram. it cannot be substituted for the reset operation by the res terminal. for more information regarding to the reset operation by the res terminal, refer to (1-8) ?reset circuits?. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 1 0 0 0 1 0 reset status by ?reset? instruction 1. page address : (0) page 2. column address : (00) h 3. initial display line : (00) h 4. contrast level set : 32 level 5. internal resistor ratio : 1+rb/ra=2.3 6. display data length : (0,0,0,0) 7. white mode set : off 8. white palette register : (0,0,0,0) 9. light gray mode set : off 10. light gray palette register : (0,0,0,0) 11. dark gray mode set : off 12. dark gray palette register : (1,1,1,1) 13. black mode set : off 14. black palette register : (1,1,1,1) 15. frc, pwm mode : 4-frame, 9-level (w) n-line inversion mode off the ?n-line inversion mode off? instruction is used to disable the n-line inversion. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 1 0 0 1 0 0 (x) display data length set the ?display data length set? instruction is used in the 3-line serial interface mode in order to specify the data length in between 1 and 256 bytes for the display data transferred to the ddram. the next transferred data after the display data is distinguished as instruction data. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 1 0 1 0 0 0 set display data length 0 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 specify the data length
26 NJU6680 - 26 - (y) frc & pwm set the ?frc & pwm set? instruction is used to specify the configuration of pwm and frc for the 4 gray scale display. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 0 1 0 frc pwm 1 pwm 0 frc frame rate 0 4-frame 1 3-frame pwm 1 pwm 0 pwm level 0 0 9-level 0 1 9-level 1 0 12-level 1 1 15-level (z) gray scale mode and register set the ?gray scale mode and register set? instruction is composed of two bytes and is used to specify the contrast level for each of the gray scale modes. the first byte specifies the gray scale mode and the frame number, and then the second byte sets pallet values into the specified 4-bit pallet register. for detailed information regarding the gray scale function, refer to (5) ?gray scale function?. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 0 0 1 0 0 0 white mode set, 1st/2nd frame 0 0 wb 3 wb 2 wb 1 wb 0 wa 3 wa 2 wa 1 wa 0 4-bit pallet registers 0 0 1 0 0 0 1 0 0 1 white mode set, 3rd/4th frame 0 0 wd 3 wd 2 wd 1 wd 0 wc 3 wc 2 wc 1 wc 0 4-bit pallet registers 0 0 1 0 0 0 1 0 1 0 light gray mode set, 1st/2nd frame 0 0 lb 3 lb 2 lb 1 lb 0 la 3 la 2 la 1 la 0 4-bit pallet registers 0 0 1 0 0 0 1 0 1 1 light gray mode set, 3rd/4th frame 0 0 ld 3 ld 2 ld 1 ld 0 lc 3 lc 2 lc 1 lc 0 4-bit pallet registers 0 0 1 0 0 0 1 1 0 0 dark gray mode set, 1st/2nd frame 0 0 db 3 db 2 db 1 db 0 da 3 da 2 da 1 da 0 4-bit pallet registers 0 0 1 0 0 0 1 1 0 1 dark gray mode set, 3rd/4th frame 0 0 dd 3 dd 2 dd 1 dd 0 dc 3 dc 2 dc 1 dc 0 4-bit pallet registers 0 0 1 0 0 0 1 1 1 0 black mode set, 1st/2nd frame 0 0 bb 3 bb 2 bb 1 bb 0 ba 3 ba 2 ba 1 ba 0 4-bit pallet registers 0 0 1 0 0 0 1 1 1 1 black mode set, 3rd/4th frame 0 0 bd 3 bd 2 bd 1 bd 0 bc 3 bc 2 bc 1 bc 0 4-bit pallet registers (aa) display mode set the ?display mode set? instruction is used to select either ?gray scale mode? or ?black & white mode?. for more information, refer to (6) ?black & white mode?. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 1 0 1 1 1 dm 0 dm 0 display mode 0 gray scale mode 1 black & white mode (bb) test mode this instruction is used only for manufacturer?s tests. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 1 1 * * * *
NJU6680 - 27 - (3) internal power circuits the internal power circuits are composed of the voltage converter, voltage regulator with 64-level evr, and voltage followers. the status of the internal power circuits is arranged by the ?power control set? instruction, as shown in table 4. for this arrangement, the part of the internal power circuits can be used in combination with an external power supply, as shown in table 5. the internal power circuits require the optimum values for the passive components, such as v0 to v4 capacitors and external feedback resistors in accordance with an lcd panel; and accordingly should be evaluated by using of actual lcd module samples to decide these values. table 4. power control set bits portions status v c voltage converter 1: on 0: off v r voltage regulator 1: on 0: off v f voltage followers 1: on 0: off table 5. power supply combinations instruction power supply circuits output terminals combination v c v r v f voltage converter voltage regulator voltage followers v out v 0 v 1 -v 4 using all internal power circuits 1 1 1 on on on open open open using voltage regulator and voltage followers 0 1 1 off on on external open open using voltage followers 0 0 1 off off on open external open using only external power supply 0 0 0 off off off open external external note) decoupling capacitors on the v 0 to v 4 terminals are required when the voltage followers are enabled.
28 NJU6680 - 28 - (3-1) voltage converter the voltage converter is designed to generate a maximum 6x voltage from the voltage difference between the v ci and v ss terminals. it is programmed so that the boost level can be selected out of 3x, 4x, 5x or 6x by the ?boost level set? instruction. since the voltage converter operates by using of the internal clocks supplied from the oscillator, the oscillator is required to be working during the voltage converter operation. the boosted voltage v out must not exceed beyond the 18.0v described in ?absolute maximum ratings?. otherwise, the voltage stress may cause a permanent damage to the lsi. fig.4 illustrates the capacitor connections for the voltage converter. fig.4 capacitors connections for the voltage converter v ci v ss v out =3x (v ci -v ss ) v ci v ss v out =4x (v ci -v ss ) v ci v ss v out =5x (v ci -v ss ) v ci v ss v out =6x (v ci -v ss ) v ss v out c 5+ c 3+ c 1- c 1+ c 2+ c 2- c 4+ 6x boost cout c 4 c 2 c 1 c 3 c 5 v ss v out c 5+ c 3+ c 1- c 1+ c 2+ c 2- c 4+ 5x boost cout c4 c2 c 1 c 3 v ss v out c 5+ c 3+ c 1- c 1+ c 2+ c 2- c 4+ 4x boost c out c 2 c 1 c 3 v ss v out c 5+ c 3+ c 1- c 1+ c 2+ c 2- c 4+ 3x boost cout c 2 c 1 [reference values: cout, c 1 to c 5 =1.0 to 4.7uf]
NJU6680 - 29 - (3-2) voltage regulator the voltage regulator is composed of the reference voltage generator, 64-level evr, operational amplifier, and internal (or external) feedback resistors, as illustrated in fig.5 and used to generate the lcd driving voltage v 0 . in the voltage regulator, the reference voltage v ref is gained with the evr to produce regulated voltage v con , which is used for the input voltage of the internal operational amplifier. namely, the v 0 is determined in accordance with the setting for the evr and internal (or external) resistor ratio, as calculated by the following equations [1] and [2]. v 0 = (1+rb/ra) x v con [1] v con = (1-(63-n)/210) x v ref [2] fig.5 voltage regulator (3-3) setting for internal resistor ratio either external or internal feedback resistors can be selected by setting the intrs terminal to ?0? or ?1?, as shown in table 6. in case that the internal resistors are used, the resistor ratio (1+rb/ra) can be selected by the ?internal resistor ratio? instruction, as listed in table 7. table 6. setting for the intrs terminal intrs ra, rb 0 external resistors 1 internal resistors table 7. setting for the intrenal resistor ratio r 2 r 1 r 0 1+(rb/ra) 0 0 0 2.3 0 0 1 3.0 0 1 0 3.7 0 1 1 4.4 1 0 0 5.1 1 0 1 5.8 1 1 0 6.5 1 1 1 7.2 (3-4) contrast control voltage vcon in the equation [2], the vcon depends on the parameter ?n?, which is determined in between 0 and 63 by the ?contrast level set? instruction. table 8. setting for the contrast level c5 c4 c3 c2 c1 c0 n v con 0 0 0 0 0 0 0 min. : : : : : : : : 1 1 1 1 1 1 63 max. v out v 0 v r v ss r b r a v con v 0 : lcd driving voltage ra, rb : feed back resistors v con : contrast control voltage n : parameter decided instruction v ref : reference voltage
30 NJU6680 - 30 - (3-5) reference voltage v ref either external or internal reference voltage v ref is selected by setting the ref terminal to ?0? or ?1?, as shown in table 9. when the internal reference voltage v ref is selected, the v ref is designed to be 2.1v typical and its temperature coefficient becomes -0.125%/ c typical. table 9. setting for the ref terminal ref v ref (v) temperature coefficient 0 external voltage on the vext terminal - 1 internal voltage (vref=2.1v typical) -0.125%/ c typical (3-6) range for the contrast control the lcd driving voltage v 0 is determined in accordance with the setting for the evr and the internal (or external) resistor ratio. fig.6 graphs the range for the contrast control using the ?contrast level set? and ?internal resistor set? instructions. fig.6 range for the contrast control 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 0 7 15 23 31 47 55 63 000 001 010 011 100 101 110 111 v 0 [v] contrast level set internal resister
NJU6680 - 31 - (3-7) using external ra and rb resistors in case that the external feedback resistors (ra, rb) are used by setting the intrs terminal to ?0?, these external resistors are required to be placed between the v ss and v r and between the v r and v 0 terminals. the lcd driving voltage v 0 is determined in accordance with the setting for the evr and the external resistor ratio (1+rb/ra) in the following equations [1] and [2], as well as the setting in using the internal resistors ra and rb. v 0 = (1+rb/ra) x v con [1] v con = (1-(63-n)/210) x v ref [2] the following calculations describe the setting example to decide the external resistors ra and rb values. requirements: 1 . lcd driving voltage v 0 =14.0v (when the contrast level parameter ?n?=32) 2.the maximum current flowing through the external ra and rb = 5ua calculations: following the equation [2], v con = (1-(63-32)/210) x 2.1v = 1.79v following the equation [1], rb/ra = v 0 /v con ? 1 = 14.0v/1.79v ? 1 = 6.821 -----[a] following the requirement 2, ra+rb = 14.0v/5ua = 2.8m ohm -----[b] finally, the values for the ra and rb are determined by the results [a] and [b], ra = 0.358m ohm rb = 2.442m ohm contrast level [n] v 0 [v] 0 11.5v : : 32 14.0v : : 63 16.4v (3-8) voltage followers the voltage followers are used to stabilize and output the lcd driving voltages (v 0 , v 1 , v 2 , v 3 and v 4 ), which are produced by the internal bleeder resistors. it can be programmed to select the lcd bias in the range of 1/5 and 1/12 by the ?lcd bias set? instruction. generally, the optimum bias ratio is determined by the following equation: lcd bias ratio=1/(1+( duty ratio)). for instance, in case of 1/80 duty cycle ratio, it should be 1/10 in accordance with the calculation: 1/(1+( 80)). when the voltage followers are used, the capacitors for the v 0 to v 4 terminals are required in order to stabilize the lcd driving voltages and should be in between 0.47uf and 2.0uf. v0 : lcd driving voltage ra, rb : feed back resistors v con : contrast control voltage n : parameter decided instruction v ref : reference voltage
32 NJU6680 - 32 - fig.7 power circuits configuration v out c 5 + c 4 + c 3 + c 2 + c 2 - c 1 - c 1 - v r v 0 v 1 v 2 v 3 v 4 intrs voltage converter v out c 5 + c 4 + c 3 + c 2 + c 2 - c 1 - c 1 - v r v0 v1 v2 v3 v4 intrs voltage converter v out c 5 + c 4 + c 3 + c 2 + c 2 - c 1 - c 1 - v r v 0 v 1 v 2 v 3 v 4 intrs external power supply v out c 5 + c 4 + c 3 + c 2 + c 2 - c 1 - c 1 - v r v 0 v 1 v 2 v 3 v 4 intrs external power supply using all internal power circuits and internal resistors using all internal power circuits and external resistors using only voltage regulator and internal resistors using only external power supply
NJU6680 - 33 - (4) mpu interface (4-1) interface type selection the interface type (the parallel or serial interface) is determined by the condition of the ps 0 and ps 1 terminals connecting to "h" or "l" level as shown in table 10.in the 3- or 4- line serial interface mode, the ?status read? instruction cannot be used. table 10 ps 0 ps 1 type cs rs e w/r data bus terminals l l 3-line serial cs * * * si,scl l h 4-line serial cs rs * * si,scl h l 80-type mpu parallel cs rs rd wr d 7 to d 0 h h 68-type mpu parallel cs rs e r/w d 7 to d 0 *:don?t care (4-2) parallel interface in the 68- or 80- type pu parellel inter face mode, the transferred data on the d 7 to d 0 terminals is processed in accordance with the polarities of the rs,e(rd),and r/w(wr) signals as shown in table 11. table 11 data distinction 68 type 80 type cs rs e r/w rd wr operation l h h h l h none l h h l h l write display data l l h h l h read out status read l l h l h l write instruction data (4-3) serial interface in the serial interface mode, when the chip select is active(cs=?0?) the si and scl are enabled. while the chip select is not active (cs=?1?), the si & scl are disabled and the internal 8-bit shift register and the 3-bit counter are being initialized. the 8-bit serial data on the si terminal is fetched at the at the rising edge of the scl signals in order of d 7 , d 6 ...d 0 data ,and the fetched data is converted into 8-bit parallel data on the 8 th scl signals. (a) 4-line serial interface in the 4-line serial interface mode, the transferred data on the si terminal is distinguished as display data or instruction data in accordance with the polarity of the rs signal at the 8th scl signal, as illustrated in fig. 8-1. fig. 8-1 4-line serial interface timing d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 cs si scl rs
34 NJU6680 - 34 - (b) 3-line serial interface in the 3-line serial interface mode, the ?display data length set? instruction is used to specify the data length in between 1 and 256 bytes for the display data transferred to the ddram. the ?display data length set? instruction is executed by 2 bytes data, after which the display data can be continuously transferred. the next transferred data after the display data is distinguished as instruction data. fig 8-2 illustrates the timing and setting example for the data transmission in the 3-line serial interface mode. when the chip select becomes non-active (cs=?1?) during a serial display data stream, the interrupted byte data is invalid, however all previous transferred display data is valid and next transferred data will be distinguished as instruction data. fig 8-2 3-line serial interface timing page address sets column address set display data length set (dual instructions) display data page msb lsb 3 bytes 2 bytes 1 ? 256 bytes display data write 0 7 8 15 16 23 0 7 8 15 0 cs scl si ? the setting example for the data transmission in the 3-line serial interface mode. page address set (1, 0, 1, 1, p 3 , p 2 , p 1 , p 0 ) column address lsb set: (0, 0, 0, 1, 0, c 6 , c 5 , c 4 ) column address msb set (0, 0, 0, 0, c 3 , c 2 , c 1 , c 0 ) display data length set (dual instructions) set display data length (1, 1, 1, 0, 1, 0, 0, 0) specify the data length (d 7 , d 6 , d 5 , d 4 , d 3 , d 2 , d 1 , d 0 ) display data write
NJU6680 - 35 - (5) gray scale function (5-1) frc (frame rate control) and pwm (pulse width modulation) the 4-gray scale function is controlled by the setting for the frc and pwm configurations and the palette values into the 4-bit palette registers, and provides required gray scale levels. this setting is executed by the ?frc & pwm set? and ?gray scale mode and register set? instructions, as described in the following. (5-2) frc & pwm set the ?frc & pwm set? instruction is used to specify the pwm and frc configurations . rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 0 1 0 frc pwm 1 pwm 0 frc frame rate 0 4-frame 1 3-frame pwm 1 pwm 0 pwm level 0 0 9-level 0 1 9-level 1 0 12-level 1 1 15-level (5-3) gray scale mode & register set the ?gray scale mode and register set? instruction is composed of two bytes and used to specify the contrast level for each of the gray scale modes. the first byte specifies the gray scale mode and frame number and then the second byte sets the pallet value into the specified 4-bit pallet register. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 0 0 1 gm 2 gm 1 gm 0 gray scale mode & frame 0 0 4-bit pallet register 4-bit pallet register 4-bit pallet register set gm 2 gm 1 gm 0 gray scale mode & frame 0 0 0 1st/2nd frame 0 0 1 white mode 3rd/4th frame 0 1 0 1st/2nd frame 0 1 1 light gray mode 3rd/4th frame 1 0 0 1st/2nd frame 1 0 1 dark gray mode 3rd/4th frame 1 1 0 1st/2nd frame 1 1 1 black mode 3rd/4th frame
36 NJU6680 - 36 - (5-4) setting tables for the frc and pwm table 12-1. gray scale table for the 4-frc gray scale level display data msb (d 7 to d 4 ) lsb (d 3 to d 0 ) 2nd frame 1st frame white 00 4th frame 3rd frame 2nd frame 1st frame light gray 01 4th frame 3rd frame 2nd frame 1st frame dark gray 10 4th frame 3rd frame 2nd frame 1st frame black 11 4th frame 3rd frame table 12-2. gray scale table for the 3-frc gray scale level display data msb (d 7 to d 4 ) lsb (d 3 to d 0 ) 2nd frame 1st frame white 00 * 3rd frame 2nd frame 1st frame light gray 01 * 3rd frame 2nd frame 1st frame dark gray 10 * 3rd frame 2nd frame 1st frame black 11 * 3rd frame note) *: don?t care. table 13. gray scale table for the pwm 4-bit palett register 9-pwm 12-pwm 15-pwm 0,0,0,0 0 0 0 0,0,0,1 1/9 1/12 1/15 0,0,1,0 2/9 2/12 2/15 0,0,1,1 3/9 3/12 3/15 0,1,0,0 4/9 4/12 4/15 0,1,0,1 5/9 5/12 5/15 0,1,1,0 6/9 6/12 6/15 0,1,1,1 7/9 7/12 7/15 1,0,0,0 8/9 8/12 8/15 1,0,0,1 1 9/12 9/15 1,0,1,0 0 10/12 10/15 1,0,1,1 0 11/12 11/15 1,1,0,0 0 1 12/15 1,1,0,1 0 0 13/15 1,1,1,0 0 0 14/15 1,1,1,1 0 0 1
NJU6680 - 37 - (6) black & white mode as an extended function, the lsi is designed to support the black & white mode, which can be switched from the gray scale mode by the ?display mode set? instruction. the gray scale mode is set in the default status . (6-1) display mode set instruction the ?display mode set? instruction is used to select either gray scale or black & white mode. it is required that the ?display off? instruction and ddram initialization are executed before the ?display mode set? instruction. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 1 1 0 1 1 1 dm 0 dm 0 display mode 0 gray scale mode 1 black & white mode (6-2) display data ram (ddram) although the ddram?s capability in the gray scale mode is 32,768-bit (128-line by 256-column) for the lcd panel with up to 128x128 pixels, the capability in the black & white mode is 16,384-bit out of the total memory area, as illustrated in the fig 9. in the black and white mode, 1-bit display data is used for 1-pixel. (6-3) column address set in the black & white mode, an mpu can access 7-bit [c6:c0] column address by the ?column address lsb set? and ?column address msb set? instructions. the column address automatically increases by 1 (+1) after each 1-byte display data. (6-4) display data length set the ?display data length set? instruction is used in the 3-line serial interface mode in order to specify the data length in between 1 and 128 bytes in the black & white mode. the d 7 bit in the ?display data length set? instruction must be ?0?. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 1 0 1 0 0 0 set display data length 0 0 (d 7 ) d 6 d 5 d 4 d 3 d 2 d 1 d 0 specify the data length (d 7 ) : must be ?0? in the black & white mode
38 NJU6680 - 38 - page address data display pattern line address common outputs d 0 00 h com 0 d 1 01 h com 1 d 2 02 h com 2 d 3 page 0 03 h com 3 d 4 04 h com 4 d 5 05 h com 5 d 6 06 h com 6 d 3 ,d 2 ,d 1 ,d 0 (0,0,0,0) d 7 07 h com 7 d 0 08 h com 8 d 1 09 h com 9 d 2 0a h com 10 d 3 page 1 0b h com 11 d 4 0c h com 12 d 5 0d h com 13 d 6 0e h com 14 d 3 ,d 2 ,d 1 ,d 0 (0,0,0,1) d 7 0f h com 15 d 0 10 h com 16 d 1 11 h com 17 d 2 12 h com 18 : : : : : : : : : : : : : : : : d 5 75 h com 117 d 6 76 h com 118 : : : : d 7 77 h com 119 d 0 78 h com 120 d 1 79 h com 121 d 2 7a h com 122 d 3 page 15 7b h com 123 d 4 7c h com 124 d 5 7d h com 125 d 6 7e h com 126 d 3 ,d 2 ,d 1 ,d 0 (1,1,1,1) d 7 7f h com 127 adc=0 00 01 02 03 04 05 06 [c6:c0] 7e 7f column address adc=1 7f 7e 7d 7c 7b 7a 79 [c6:c0] 01 00 segment outputs 0 1 2 3 4 5 6 ?????????.. 126 127 fig.9 display data ram (ddram) map in the black & white mode this is an example for initial display line (06) h . initial=(06) h
NJU6680 - 39 - (7) partial display function the partial display function is used to specify optimum duty cycle ratio, lcd bias ratio, boost level and lcd driving voltage to partially display active area on an lcd panel, so that it is possible to display the time and calendar under extremely low power consumption state. it can be programmed to select the duty cycle ratio, lcd bias ratio, boost level and evr level by the instructions. fig.10-1 illustrates normal display image and fig.10-2, 10-3 and 10-4 illustrate the partial display images. the setting sequence for the partial display is described in fig.15. fig.10-1 normal display image (duty cycle ratio=1/128, com 0 =0) fig.10-2 partial display image 1 (duty cycle ratio=1/120, com 0 =0) com8 com9 com15 com112 com119 com120 com127 com0 com8 com9 com15 com112 com119 com120 com127 com0 com8 com9 com15 com112 com119 com120 com127 com0 com8 com9 com15 com112 com119 com120 com127
40 NJU6680 - 40 - fig.10-3 partial display image 2 (duty cycle ratio=1/16, com 0 =112) fig.10-4 partial display image 3 (duty cycle ratio=1/112, com 0 =9) com0 com8 com9 com15 com112 com119 com120 com127 com0 com8 com9 com15 com112 com119 com120 com127 com0 com8 com9 com15 com112 com119 com120 com127 com0 com8 com9 com15 com112 com119 com120 com127
NJU6680 - 41 - examples for instruction sequence fig.11 initialization in using the internal power circuits start of initialization power on (v dd -v ss ) with keeping res=l wait for the power on (v dd -v ss ) stabilization res=h adc select com scan direction select partial display duty set initial com0 line set internal oscillator on boost level set lcd bias set internal resistor ratio set contrast level set power control set (v c =v r =v f =1) wait for lcd power supply stabilization end of initialization frc & pwm set gray scale mode and register set n-line inversion set
42 NJU6680 - 42 - fig.12 initialization in using the external power supply start of initialization power on (v dd -v ss ) with keeping res=l wait for the power on (v dd -v ss ) stabilization power save mode on adc select com scan direction select partial display duty set initial com 0 line set internal oscillator on power control set (v c =v r =v f =0) frc & pwm set gray scale mode and register set n-line inversion set wait for lcd power supply stabilization end of initialization res=h external save mode on power save mode off
NJU6680 - 43 - fig.13 display data write sequence fig.14 power off sequence end of display data write end of initialization initial display line set page address set column address set display data write display on optional status end of power off (v dd -v ss ) power save mode on power off (v dd -v ss )
44 NJU6680 - 44 - fig.15 partial display sequence end of initialization optional status display off power save mode on partial display duty set initial display line set initial com 0 line set boost level set lcd bias set internal resistor ratio set contrast level set frc & pwm set gray scale mode and register set n-line inversion set wait for lcd power supply stabilization power save mode off display data write 1display on
NJU6680 - 45 - absolute maximum rating (ta=-25 c) parameter symbol ratings unit supply voltage(1) v dd , v ci -0.3 to +4.0 v supply voltage(2) v 0 , v out v ss -0.3 to v ss +18.0 v supply voltage(3) v 1 ,v 2 ,v 3 ,v 4 -0.3 to v 0 +0.3 v input voltage v in -0.3 to v dd +0.3 v operating temperature t opr -30 to +80 c tcp -55 to +100 strage temperature chip t stg -55 to +125 c note 1) all voltages are relative to v ss =0v reference. the relationship among the supply voltages should be maintained in the following condition: v ss < v 4 < v 3 < v 2 < v 1 < v 0 < v out . note 2) when the external power supply is used for the lcd driving voltages, the external power supply should be turn on at the same timing or after the timing that the v dd is turned on. note 3) the lsi should be operated inside of the ?absolute maximum ratings? in order to prevent excessive stress. otherwise, the stresses beyond the ?absolute maximum ratings? may cause a permanent damage to the lsi. note 4) the decoupling capacitors between the v dd , v ci , and v ss terminals are required in order to stabilize the lsi operation. v 0 v ss v ss v ci
46 NJU6680 - 46 - electrical characteristics (v dd =2.0 to 3.0v, v ss =0v, ta=-30 to +80 c) parameter symbol conditions min typ max unit note 2.0 3.0 operating voltage(1) v dd v dd =2.7v 2.7 2.775 2.875 v 5 operating voltage(2) v ci v dd 3.0 v 0 6.0 15.0 v 1 ,v 2 0.6v 0 v 0 operating voltage(3) v 3 ,v 4 v lcd =v 0 -v ss v ss 0.4v 0 v high level v ih 0.8v dd v dd input voltage low level v il v ss 0.2v dd v high level v oh i oh =-0.5ma 0.8v dd v dd output voltage low level v ol d 0 to d 1 terminal i ol = 0.5ma v ss 0.2v dd v input leakage current i li -1.0 1.0 a output leakage current i l0 -3.0 3.0 a driver on-resistance r on v 0 =8.0v 3.0 4.5 k ? 6 stand-by current i sleep in power save mode 2.0 a 7 input terminal capacitance c in ta=25 c 10 pf 8 frame frequency f fr rf=270k ? 150 180 hz reset time t r res terminal 1.0 s 9 reset ?l? level pulse width t rw 10 s 10 input voltage v ci v dd -v ss 6-times boost v dd 3.0 v 11 voltage converter efficiency no-load 95 99 % voltage follower operating voltage v 0 voltage regulator ?off? 6.0 16.5 v voltage converter output on resustance r step c 1 to c 5 , c out =1.0 f 6-times boost 2.0 4.0 k ? operating current i out1 ta=25 c, v dd =2.75v (checker board display, no access from mpu, all com/seg open) 400 550 a 13 reference voltage v ref ta=25 c 2.04 2.10 2.16 v external reference voltage v ext 2.0 v dd v v ref temp.coefficient tc v dd =3.0v -0.125 %/ c
NJU6680 - 47 - note 5) this parameter cannot be guaranteed for the spike voltage during an mpu access. note 6) apply to the resistance between each driver (com, seg) and power supply (v 1 ,v 2 ,v 3 ,v 4 ) terminals when the voltage difference 0.1v is supplied between these terminals. note 7) apply to the condition when the internal power circuits are not used and mpu doesn?t access to the lsi. note 8) apply to the d 7 to d 0 , e, r/w, rs, cs, ps 0 and ps 1 terminals. note 9) specified the time between the rising edge of the res signal and the completion of the reset operation. note 10) specify the minimum pulse width of the res signal. note 11) apply to the v dd when 6x boost level is used. note 12) the lcd driving voltage can be adjusted within the operating range of the voltage converter. note 13) each of the values is specified by each of the following conditions. power supply set instruction operating condition symbol vc vr vf voltage converter voltage regulator voltage follower i out1 1 1 1 on (5 times) on on
48 NJU6680 - 48 - bus timing characteristics ? read/write operation sequence(80 type mpu) (v ss =0v, v dd =2.0v, ta=-30 to 80 c) parameter signal symbol measurement condition min max unit address set up time t aw 8 0 address hold time t ah8 0 system cycle time rs,cs t cyc8 330 read t cchr 210 control ?h? pulse width write t cchw 210 read t cclr 120 control ?l? pulse width write wr,rd t cclw 60 data set up time t ds8 40 data hold time t dh8 15 rd access time t acc8 114 output disable time d 7 to d 0 t oh8 cl=100pf 5 21 input signal rising, falling edge tr,tf 15 ns (v ss =0v, v dd =2.7v, ta=-30 to 80 c) parameter signal symbol measurement condition min max unit address set up time t aw 8 0 address hold time t ah8 0 system cycle time rs,cs t cyc8 166 read t cchr 70 control ?h? pulse width write t cchw 70 read t cclr 70 control ?l? pulse width write wr,rd t cclw 30 data set up time t ds8 30 data hold time t dh8 10 rd access time t acc8 50 output disable time d 7 to d 0 t oh8 cl=100pf 2 9 input signal rising, falling edge tr,tf 15 ns tf t aw 8 wr,rd rs,csb d7 to d0 write d7 to d0 read t cyc8 t ccl t ah8 t dh8 t oh8 t ds8 t acc8 tr t cch
NJU6680 - 49 - ? system bus sequence (read / write) (68-type 1 mpu) (v ss =0v, v dd =2.0v, ta=-30 to 80 c) parameter signal symbol measurement condition min max unit address set up time t aw 6 0 address hold time t ah6 0 system cycle time rs,cs t cyc6 350 data set up time t ds6 40 data hold time t dh6 10 rd access time t acc6 128 output disable time d 7 to d 0 t oh6 cl=100pf 5 35 input signal rising, falling edge tr,tf 15 ns (v ss =0v, v dd =2.7v, ta=-30 to 80 c) parameter signal symbol measurement condition min max unit address set up time t aw 6 0 address hold time t ah6 0 system cycle time rs,cs t cyc6 166 data set up time t ds6 30 data hold time t dh6 5 rd access time t acc6 52 output disable time d 7 to d 0 t oh6 cl=100pf 4 15 input signal rising, falling edge tr,tf 15 ns note 14) apply to the condition that e pin is always fixed to ?h?. csb d7 to d0 write d7 to d0 read taw6 tah6 tdh6 toh6 tds6 tacc6 tr r/w rs tf
50 NJU6680 - 50 - ? system bus sequence (read / write) (68-type 2 mpu) (v ss =0v, v dd =2.0v, ta=-30 to 80 c) parameter signal symbol measurement condition min max unit address set up time t aw 6 0 address hold time t ah6 0 system cycle time rs,cs t cyc6 350 read t cchr 140 enable ?h? pulse width write t cchw 60 read t cclr 210 enable ?l? pulse width write e t cclw 210 data set up time t ds6 40 data hold time t dh6 10 rd access time t acc6 128 output disable time d 7 to d 0 t oh6 cl=100pf 5 35 input signal rising, falling edge tr, tf 15 ns (v ss =0v, v dd =2.7v, ta=-30 to 80 c) parameter signal symbol measurement condition min max unit address set up time t aw 6 0 address hold time t ah6 0 system cycle time rs,cs t cyc6 166 read t cchr 70 enable ?h? pulse width write t cchw 30 read t cclr 70 enable ?l? pulse width write e t cclw 70 data set up time t ds6 30 data hold time t dh6 5 rd access time t acc6 52 output disable time d 7 to d 0 t oh6 cl=100pf 4 15 input signal rising, falling edge tr,tf 15 ns t cyc6 tr e r/w d7 to d0 write d7 to d0 read t dh6 t oh6 t ds6 t aw 6 t ccl t ah6 t acc6 tf t cch
NJU6680 - 51 - ? serial interfave (v ss =0v, v dd =2.0v, ta=-30 to 80 c) parameter signal symbol measurement condition min max unit serial clock cycle t scyc 110 scl ?h? pulse width t shw 40 scl ?l? pulse width scl t slw 40 address set up time t sas 60 address hold time rs t sah 60 data set up time t sds 50 data hold time si t sdh 60 t css 60 cs-scl time cs t csh 55 rising, falling edge tr,tf 15 ns (v ss =0v, v dd =2.7v, ta=-30 to 80 c) parameter signal symbol measurement condition min max unit serial clock cycle t scyc 55 scl ?h? pulse width t shw 20 scl ?l? pulse width scl t slw 20 address set up time t sas 30 address hold time rs t sah 30 data set up time t sds 25 data hold time si t sdh 30 t css 30 cs-scl time cs t csh 27 rising, falling edge tr,tf 15 ns note 15) spi clock tolerance is 2ppm. cs rs scl si t css t slw t sah t shw t sdh t sds tr tf t scyc t csh t sas
52 NJU6680 - 52 - lcd driving wave form (black & white mode) c0-s1 c0-s0 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 s0 s1 s2 s3 s4 fr c1 s1 s0 c0 c2 v dd v ss v 0 v 1 v 2 v 3 v 4 v ss v 0 v 1 v 2 v 3 v 4 v ss v 0 v 1 v 2 v 3 v 4 v ss v 0 v 1 v 2 v 3 v 4 v ss v 0 v 1 v 2 v 3 v 4 v ss v 0 v 1 v 2 v 3 v 4 v ss -v 4 -v 3 -v 2 -v 1 -v 0 v 0 v 1 v 2 v 3 v 4 v ss -v 4 -v 3 -v 2 -v 1 -v 0
NJU6680 - 53 - application circuit example for the application circuits in using the internal power circuits (vc=vr=vf=1) fig.16 reference values: rf cout c1 ? c5 c6 ra, rb setting example: note1) ps 0 =ps 1 =1 note2) ref=1 note3) intrs=0 : 270k ? for ffr=165hz(typ.) : 1.0[ uf ] ? 4.7[ uf ] : 1.0[ uf ] ? 4.7[ uf ] : 0.47[ uf ] ? 2.0[ uf ] : refer to (3-7) using external ra and rb resistors : 68 type mpu interface : internal reference voltage : external ra and rb resistors reference values: rf cout c1 ? c5 c6 : 1.0[ uf ] ? 4.7[ uf ] : 1.0[ uf ] ? 4.7[ uf ] : 0.47[ uf ] ? 2.0[ uf ] rb ps0 ps1 csb resb rs r/w e db7 - 0 vdd vci vss + 68 type mpu ( note1) vdd vss + ps0 ps1 csb resb rs r/w e db7 - 0 vdd vci vss + 68 type mpu ( note1) vdd vss vout c5+ c3+ c1 - c1+ c2+ c2 - c4+ ref vext intrs v4 v3 v2 v1 v0 vr osc1 + + + + + + + + + + + com0 - 127 lcd panel 128 x 128 pixels NJU6680 c3 cout c5 c1 c2 c4 c6 c6 c6 c6 ra c6 rb rf ( note2) ( note3) seg0 - 127 vout c5+ c3+ c1 - c1+ c2+ c2 - c4+ ref vext intrs v4 v3 v2 v1 v0 vr osc1 + + + + + + + + + + + com0 - 127 lcd panel 128 x 128 pixels c3 cout c5 c1 c2 c4 c6 c6 c6 c6 ra c6 rb rf ( note2) ( note3) seg0 - 127 +
54 NJU6680 - 54 - ? mpu interface example ? 80 type mpu ? 68 type mpu ? serial interface (4-wire) ? serial interface (3-wire) ps1= decoder a0 a1 ? a7 /iorq d7 ? d0 /rd /wr /reset reset vcc vss vdd vss mpu NJU6680 rs csb d7 ? d0 rdb wrb resb ps0 ps1 ps0= ? 1 ? ? 1 ? decoder a0 a1 ? a7 /iorq d7 ? d0 /rd /wr /reset reset v cc v ss v dd v ss mpu NJU6680 rs cs d7 ? d0 rd wr res ps0 ps1 ps0= ? 1 ? ? 1 ? decoder a0 a1 ? a7 vma d7 ? d0 e r/w /reset reset vcc vss vdd vss mpu NJU6680 rs csb d7 ? d0 e r/w resb ps0 ps1 ps0= ? 1 ? ps1= ? 0 ? decoder a0 a1 ? a7 vma d7 ? d0 e r/w /reset reset v cc v ss v dd v ss mpu NJU6680 rs cs d7 ? d0 e r/w res ps0 ps1 ps0= ? 1 ? ps1= ? 0 ? decoder a0 a1 ? a7 port1 port2 /reset reset vcc vss vdd vss mpu NJU6680 rs csb si scl resb ps0 ps1 ps0= ? 0 ? ps1= ? 1 ? decoder a0 a1 ? a7 port1 port2 /reset reset v cc v ss v dd v ss mpu NJU6680 rs cs si scl res ps0 ps1 ps0= ? 0 ? ps1= ? 1 ? decoder a1 ? a7 port1 port2 /reset reset vcc vss vdd vss mpu NJU6680 csb si scl resb ps0 ps1 ps0= ? 0 ? ps1= ? 0 ? decoder a1 ? a7 port1 port2 /reset reset v cc v ss v dd v ss mpu NJU6680 cs si scl res ps0 ps1 ps0= ? 0 ? ps1= ? 0 ?
NJU6680 - 55 - ? connections between the lsi and lcd panel (1) adc=0, com scan direction=0 (2) adc=1, com scan direction=0 (3) adc=1, com scan direction=1 (4) adc=0, com scan direction=1 fig. 17 seg127 com64 com127 NJU6680 (top view) 128 x128 pixels ( com scan direction) com0 com63 seg0 seg127 com64 com127 NJU6680 (top view) 128 x128 pixels ( com scan direction) com0 com63 seg0 seg127 seg0 com64 com127 com0 com63 NJU6680 (bottom view) 128 x128 pixels ( com scan direction) seg127 seg0 com64 com127 com0 com63 NJU6680 (bottom view) 128 x128 pixels ( com scan direction) seg127 seg0 com64 com127 com0 com63 NJU6680 (top view) 128 x128 pixels ( com scan direction) seg127 seg0 com64 com127 com0 com63 NJU6680 (top view) 128 x128 pixels ( com scan direction) seg0 seg127 com0 com63 com64 com127 NJU6680 (bottom view) 128 x128 pixels ( com scan direction) seg0 seg127 com0 com63 com64 com127 NJU6680 (bottom view) 128 x128 pixels ( com scan direction)
56 NJU6680 - 56 - memo [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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